/**
  ******************************************************************************
  * @file    gt32f030_iwdg.c
  * @author  GT Application Team
  * @version V1.0.0
  * @date    03-January-2025
  *       
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; COPYRIGHT 2022 Giantec Semicondutor Inc</center></h2>
  *
  *             http://www.giantec-semi.com/
  *
  * Unless required by applicable law or agreed to in writing, software 
  * distributed under the License is distributed on an "AS IS" BASIS, 
  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  * See the License for the specific language governing permissions and
  * limitations under the License.
  *
  ******************************************************************************
  */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GT32F030_IWDG_H
#define __GT32F030_IWDG_H

#ifdef __cplusplus
 extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "gt32f030.h"

/** @addtogroup GT32F030_StdPeriph_Driver
  * @{
  */

/** @addtogroup IWDG
  * @{
  */ 

/* Exported macro ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/

/** @defgroup IWDG_Exported_Constants
  * @{
  */ 
#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFFFF)
	 
/** @defgroup IWDG_OperationCmd 
  * @{
  */ 
typedef enum
{ 
  IWDG_Cmd_Srart = 0x55,
  IWDG_Cmd_Feed  = 0xAA
}IWDGCmd_TypeDef;
#define IS_IWDG_CMD(CMD) (((CMD) == IWDG_Cmd_Srart) || \
                          ((CMD) == IWDG_Cmd_Feed))
/**
  * @}
  */ 


/** @defgroup IWDG_OperationCmd 
  * @{
  */
typedef enum
{ 
  IWDG_ActiveMode_Reset      = 0x00,
  IWDG_ActiveMode_Interrupt  = 0x01
}IWDGActiveMode_TypeDef;
#define IS_IWDG_ACTMODE(ACTMODE) (((ACTMODE) == IWDG_ActiveMode_Reset)     || \
                                  ((ACTMODE) == IWDG_ActiveMode_Interrupt))
/**
  * @}
  */ 

/** @defgroup IWDG_IT 
  * @{
  */
#define IWDG_INTMask_Enable   0x00
#define IWDG_INTMask_Disable  0x02
#define IS_IWDG_INTMASK(INTMASK) (((INTMASK) == IWDG_INTMask_Enable) || \
                                  ((INTMASK) == IWDG_INTMask_Disable))
/**
  * @}
  */ 

/**
  * @}
  */


/* Exported types ------------------------------------------------------------*/
/** 
  * @brief   IWDG Init structure definition  
  */  
typedef struct 
{
  unsigned int IWDG_ReloadVal; 
  unsigned int IWDG_INTMask; 	
  IWDGActiveMode_TypeDef IWDG_ActiveMode;                 
}IWDG_InitTypeDef;


/* Exported functions --------------------------------------------------------*/
void IWDG_Init(IWDG_InitTypeDef* IWDG_InitStruct);
void IWDG_StructInit(IWDG_InitTypeDef* IWDG_InitStruct);

void IWDG_Unlock(void);
void IWDG_Lock(void);
void IWDG_SetExecuteCommand(unsigned int ExeCmd);
void IWDG_SetReloadVal(unsigned int Reload);
unsigned int IWDG_GetCountVal(void);

ITStatus IWDG_GetIT(void);
void IWDG_ClearIT(void);
FlagStatus IWDG_GetRunningStatus(void);

#ifdef __cplusplus
}
#endif

#endif /* __GT32F030_IWDG_H */

/**
  * @}
  */ 

/**
  * @}
  */ 

/************************ (C) COPYRIGHT Giantec Semicondutor Inc *****END OF FILE****/
